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The present invention relates to a memory controller and an associated multi-bank synchronous dynamic random access memory (SDRAM) device and, more particularly, to a memory controller for a multi-bank SDRAM device which implements a 1:1 state machine-to-memory bank ratio to enhance the scalability thereof.
In recent years, multi-bank memory devices such as double data rate (DDR) SDRAMS have become increasingly common. One advantage to using DDR SDRAMS and other multi-bank memory devices is that each bank of the multi-bank memory device can have a row active at the same time. As a result, when one bank of the memory device needs to conduct a time consuming operation, for example, switching between rows, the memory device may still conduct operations using an active row from another bank. Thus, at any given time, different banks of a multi-bank memory device may independently conduct different operations.
Operations performed using the various banks of a multi-bank memory device are coordinated by a controller. To perform this function, the controller includes a state machine which maintains a map of the various states of the memory device. Heretofore, multi-bank memory devices have typically employed a single state machine, regardless of the number of memory banks to be serviced thereby. As each bank of a conventional multi-bank may be in a different state, as the number of banks in the memory device increase, so has the number of different states which must be mapped to the state machine. Thus, each time a memory device having a different number of memory banks is proposed, a new state machine must be designed to service those banks. As a result, when designing a new multi-bank memory device, significant resources must be dedicated to design a state machine capable of servicing the new memory bank configuration. Furthermore, as memory devices with increasing numbers of memory banks are proposed, the cost and time incurred in re-designing state machines to service the greater number of banks is only expected to increase.
For these reasons, it would be desirable to have a memory controller readily scalable for use in multi-bank memory devices having various numbers of memory banks.
In one embodiment, the present invention is directed to a computer system having a processor, a memory having a plurality of memory banks and a memory controller for coupling the processor with the memory banks. The memory controller includes a plurality of state machines configured to commonly receive a state machine instruction and a memory address. Each one of the plurality of state machines corresponds to one of the plurality of memory banks. A first one of the plurality of state machines executes the state machine instruction if the memory address corresponds to an address for the corresponding one of the memory banks.
In another embodiment, the present invention is directed to a computer system having a processor, a memory having a plurality of memory banks and a memory controller for coupling the processor with the memory banks. The memory controller includes an input command decoder circuit coupled to receive a raw command from the processor and generate an input command therefrom, a state machine controller coupled to receive the input command from the input command decoder circuit and generate a state machine input instruction therefrom, a state machine array comprised of a plurality of state machines, each corresponding to one of the memory banks, the state machine array coupled to receive input commands and state machine input instructions from the state machine controller and generate state machine output instructions therefrom, and an output command decoder circuit for receiving a state machine output command and generating an output command therefrom for transmission to the memory. A first one of the plurality of state machines executes a state machine input instruction transmitted to each one of the plurality of state machines if a memory address contained within the input command transmitted to each one of the plurality of state machines corresponds to an address for the corresponding one of the memory banks.
In still another embodiment, the present invention is directed to a computer system having a processor, a memory having a plurality of memory banks and a memory controller for coupling the processor with the memory banks. The memory controller includes an input command decoder circuit coupled to receive a raw command from the processor and generate an input command therefrom, a state machine controller coupled to receive the input command from the input command decoder circuit and generate a state machine input instruction therefrom, a state machine array comprised of a plurality of state machines, each corresponding to one of the memory banks, the state machine array coupled to receive the input commands from the input command decoder circuit, receive state machine input instructions from the state machine controller and generate state machine output instructions from the state machine input instructions, and an output command decoder circuit for receiving a state machine output command and generating an output command therefrom for transmission to the memory. A first one of the plurality of state machines executes a state machine input instruction transmitted to each one of the plurality of state machines if a memory address contained within the input command received from the input command decoder circuit corresponds to an address for the corresponding one of the memory banks.
In still yet another embodiment, the present invention is directed to a multi-bank memory device comprised of a plurality of memory banks and a state machine array coupled to the plurality of memory banks. The state machine array includes a plurality of state machines, each controlling the state of a corresponding one of the plurality of memory banks. The multi-bank memory device is arranged to have a state machine-to-memory bank ratio of 1:1. In various further aspects thereof, the multi-bank memory device may be a SDRAM or DDR SDRAM device.
In other aspects thereof, the multi-bank memory device further includes a state machine controller, coupled to an input side of the state machine array, for generating a state machine instruction from an input command received thereby and selectively transmitting the generated state machine instruction to the plurality of state machines of the state machine array. The state machine controller may also transmit, with the state machine input instruction, the input command to the plurality of state machines of the state machine array. In this aspect, a first one of the plurality of state machines executes the state machine instruction if a memory address contained in the input command corresponds to an address for the corresponding one of the plurality of memory banks. Alternately, each one of the plurality of state machines of the state machine array and the state machine controller may commonly receive the input command.
In certain aspects of these embodiments of the invention, each one of the plurality of state machines is configured in accordance with a common state diagram. The common state diagram may be comprised of first and second portions, the first containing bank-specific states and the second containing shared states. In further aspects thereof, the memory controller may be further configured such that: (1) the state machine controller generates the state machine output command if the state machine input command would cause a state machine configured in accordance with the common state diagram to enter or exit one of the shared states and/or (2) the state machine controller generates the state machine output command if the state machine input command would cause a state machine configured in accordance with the common state diagram to transition between first and second ones of the bank-specific states.
In still another embodiment, the present invention is directed to a method for constructing a memory device by providing a first plurality of state machines and a second plurality of memory banks and coupling the first plurality of state machines to the second plurality of memory banks such that each one of the first plurality of state machines controls the state of a corresponding one of the second plurality of memory banks and that the first plurality of state machines and the second plurality of memory banks are interconnected in a state machine-to-memory bank ratio of 1:1.